1. Field of the Invention
The present invention relates to the testing of semiconductor integrated circuit chips, more particularly to the testing of semiconductor integrated circuit chips having a package with a grid array of terminals on one surface.
2. Description of the Related Art
In the field of semiconductor integrated circuit chip packaging, there has been a growing demand for smaller and thinner packages. This has led to the development of the chip scale package (CSP), which is the same size as the chip itself, or only slightly larger. This type of package can be formed in the wafer processing stage, before the wafer is diced into chips, in which case the package is referred to as a wafer-level chip scale package (W-CSP). Chip scale packages normally have a grid array of hemispherical terminals on one surface of the package, and are sometimes referred to as area array packages. The hemispherical terminals are formed on the ends of conductive posts that lead from the package surface through a sealing layer to the circuitry below.
The electrical characteristics of a semiconductor integrated circuit chip in an area array package are normally tested after the hemispherical terminals have been formed, by establishing electrical contact between the hemispherical terminals and a set of electrodes referred to as probe pins, probe needles, pogo pins, or cantilevers, and measuring the electrical characteristics of the circuit elements inside the chip. The probe pins are also used to ‘burn in’ the chip by operating it at an elevated temperature.
One problem with this testing method is that for environmental reasons, the hemispherical terminals are now generally made of a lead-free solder, which has a comparatively high contact resistance. Consequently, analog electrical characteristics such as the on-resistance of transistors cannot be measured accurately, so an extra pass-fail margin has to be allowed to provide for measurement error, and production yields are reduced accordingly.
Another problem is that the hemispherical terminals may be deformed during the burn-in process.
In a test method disclosed by Wakabayashi et al. in Japanese Patent Application Publication No. 2005-123291 (now Japanese Patent No. 3757971), the burn-in procedure is carried out in the wafer state, after the conductive posts and the sealing layer have been formed, by touching the probe pins to the ends of the conductive posts. After burn-in, the hemispherical terminals are formed as solder bumps, and then the electrical tests are carried out by touching the probe pins to the hemispherical terminals. This procedure avoids deformation of the hemispherical terminals during the burn-in process, but does not solve the problem of contact resistance and measurement error during the electrical tests.
In a test method disclosed by Nakano et al. in Japanese Patent Application Publication No. 2005-136056, contact between the probe pins and the hemispherical terminals is avoided completely by conducting the electrical tests at an intermediate stage of the packaging process before the hemispherical terminals are formed. The probe pins touch either the conductive posts or a layer of redistribution traces on which the conductive posts are seated. After electrical tests have been completed, the redistribution traces and posts are covered with a dielectric layer and a passivation layer, holes are formed in the passivation layer, and hemispherical terminals are formed in the holes to complete the package. The problem of contact resistance is thereby avoided, but since the electrical tests are carried out while the wafer is still in process, electrical problems that may arise in subsequent processing steps go undetected. More specifically, problems that arise during the formation of the dielectric and passivation layers and in particular during the opening of holes in the passivation layer and the formation of the hemispherical terminals go undetected.